{"id":2807,"date":"2025-07-25T10:30:12","date_gmt":"2025-07-25T09:30:12","guid":{"rendered":"https:\/\/workboot.fr\/ciela\/?page_id=2807"},"modified":"2025-07-25T10:31:41","modified_gmt":"2025-07-25T09:31:41","slug":"riscv","status":"publish","type":"page","link":"https:\/\/workboot.fr\/ciela\/riscv\/","title":{"rendered":"RISCV"},"content":{"rendered":"\n

Introduction \u00e0 RISC-V<\/strong><\/h2>\n\n\n\n

Qu’est-ce que RISC-V ?<\/strong><\/h3>\n\n\n\n
    \n
  • Architecture RISC (Reduced Instruction Set Computer)<\/strong>\u00a0: Jeu d’instructions simplifi\u00e9 pour une meilleure efficacit\u00e9.<\/li>\n\n\n\n
  • Open-source et libre de droits<\/strong>\u00a0: Contrairement \u00e0 ARM et x86, RISC-V peut \u00eatre utilis\u00e9 sans licence propri\u00e9taire.<\/li>\n\n\n\n
  • Modulaire et extensible<\/strong>\u00a0: Possibilit\u00e9 d’ajouter des extensions personnalis\u00e9es.<\/li>\n<\/ul>\n\n\n\n

    Origine<\/strong><\/h3>\n\n\n\n
      \n
    • D\u00e9velopp\u00e9 \u00e0 l’Universit\u00e9 de Californie, Berkeley<\/strong>\u00a0(2010).<\/li>\n\n\n\n
    • G\u00e9r\u00e9 par la\u00a0RISC-V International Foundation<\/strong>\u00a0(standardisation).<\/li>\n<\/ul>\n\n\n\n

      Pourquoi RISC-V est important ?<\/strong><\/h2>\n\n\n\n

      \u2705 Pas de royalties<\/strong> \u2192 Id\u00e9al pour les startups et l’innovation.
      \u2705 Flexibilit\u00e9<\/strong> \u2192 Adaptable aux besoins (IoT, IA, supercalculateurs).
      \u2705 \u00c9cosyst\u00e8me en croissance<\/strong> \u2192 Soutenu par Google, NVIDIA, Qualcomm, Alibaba, etc.
      \u274c Moins mature qu’ARM\/x86<\/strong> \u2192 Manque encore de logiciels et outils optimis\u00e9s.<\/p>\n\n\n\n

      Architecture de base<\/strong><\/h2>\n\n\n\n

      Jeu d’instructions (ISA)<\/strong><\/h3>\n\n\n\n
        \n
      • Base enti\u00e8re (I)<\/strong>\u00a0: Op\u00e9rations arithm\u00e9tiques, sauts, acc\u00e8s m\u00e9moire.<\/li>\n\n\n\n
      • Extensions standards<\/strong>\u00a0:\n
          \n
        • M<\/strong>\u00a0(Multiplication\/division)<\/li>\n\n\n\n
        • A<\/strong>\u00a0(Atomiques)<\/li>\n\n\n\n
        • F\/D<\/strong>\u00a0(Flottant simple\/double pr\u00e9cision)<\/li>\n\n\n\n
        • C<\/strong>\u00a0(Compression d’instructions)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n

          Exemple : RV32IMAC<\/strong> = 32 bits + extensions M, A, C.<\/p>\n\n\n\n

          Registres<\/strong><\/h3>\n\n\n\n
            \n
          • 32 registres entiers (x0-x31)<\/strong>\n
              \n
            • x0<\/strong>\u00a0: Toujours \u00e9gal \u00e0 0 (registre \u00ab\u00a0zero\u00a0\u00bb).<\/li>\n\n\n\n
            • x1 (ra)<\/strong>\u00a0: Return Address (adresse de retour).<\/li>\n\n\n\n
            • x2 (sp)<\/strong>\u00a0: Stack Pointer.<\/li>\n\n\n\n
            • x10-x17 (a0-a7)<\/strong>\u00a0: Arguments de fonctions.<\/li>\n<\/ul>\n<\/li>\n\n\n\n
            • PC (Program Counter)<\/strong>\u00a0: Pointeur d’instruction.<\/li>\n<\/ul>\n\n\n\n

              Exemple de code assembleur RISC-V<\/h2>\n\n\n\n
              addi x1, x0, 42    # x1 = 0 + 42\nadd x2, x1, x1     # x2 = x1 + x1\nlw x3, 0(x2)       # Charge en x3 la valeur \u00e0 l'adresse m\u00e9moire [x2 + 0]\njal ra, fonction   # Saut vers une fonction (ra = adresse de retour)<\/code><\/pre>\n\n\n\n
              Instructions courantes<\/strong><\/h3>\n\n\n\n
              Instruction<\/th>Description<\/th><\/tr><\/thead>
              addi rd, rs1, imm<\/code><\/td>Addition avec imm\u00e9diat<\/td><\/tr>
              lw rd, offset(rs1)<\/code><\/td>Chargement mot (32 bits)<\/td><\/tr>
              sw rs2, offset(rs1)<\/code><\/td>Stockage mot<\/td><\/tr>
              jal rd, label<\/code><\/td>Saut et lien (call)<\/td><\/tr>
              beq rs1, rs2, label<\/code><\/td>Branchement si \u00e9gal<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
              RISC-V vs ARM vs x86<\/strong><\/h2>\n\n\n\n
              Crit\u00e8re<\/strong><\/th>RISC-V<\/strong><\/th>ARM<\/strong><\/th>x86<\/strong><\/th><\/tr><\/thead>
              Licence<\/strong><\/td>Open-source<\/td>Payante (ARM Ltd.)<\/td>Propri\u00e9taire (Intel\/AMD)<\/td><\/tr>
              Flexibilit\u00e9<\/strong><\/td>Extensions libres<\/td>Modulaire (Cortex)<\/td>Peu flexible<\/td><\/tr>
              \u00c9cosyst\u00e8me<\/strong><\/td>En d\u00e9veloppement<\/td>Tr\u00e8s mature<\/td>Dominant (PC\/serveurs)<\/td><\/tr>
              Performances<\/strong><\/td>Variable (d\u00e9pend des impl\u00e9mentations)<\/td>Optimis\u00e9 mobile<\/td>Optimis\u00e9 haute perf<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
              Impl\u00e9mentations populaires<\/strong><\/h2>\n\n\n\n
                \n
              • Kendryte K210<\/strong>\u00a0: Pour l’IoT et l’IA embarqu\u00e9e.<\/li>\n\n\n\n
              • SiFive Freedom<\/strong>\u00a0: Cores RISC-V pour applications g\u00e9n\u00e9ralistes.<\/li>\n\n\n\n
              • Alibaba T-Head<\/strong>\u00a0: Processeurs pour serveurs cloud.<\/li>\n\n\n\n
              • Raspberry Pi-like<\/strong>\u00a0: Cartes comme\u00a0HiFive Unleashed<\/strong>.<\/li>\n<\/ul>\n\n\n\n
                Conclusion<\/strong><\/h3>\n\n\n\n
                RISC-V est une alternative libre et puissante<\/strong> face \u00e0 ARM et x86, id\u00e9ale pour l’embarqu\u00e9, l’IoT et les architectures personnalis\u00e9es. Son adoption croissante pourrait changer l’industrie des semi-conducteurs !<\/p>\n","protected":false},"excerpt":{"rendered":"
                Introduction \u00e0 RISC-V Qu’est-ce que RISC-V ? Origine Pourquoi RISC-V est important ? \u2705 Pas de royalties \u2192 Id\u00e9al pour les startups et l’innovation.\u2705 Flexibilit\u00e9 \u2192 Adaptable aux besoins (IoT, IA, supercalculateurs).\u2705 \u00c9cosyst\u00e8me en croissance \u2192 […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_crdt_document":"","_uag_custom_page_level_css":"","footnotes":""},"class_list":["post-2807","page","type-page","status-publish","hentry"],"yoast_head":"\nRISCV - workboot<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/workboot.fr\/ciela\/riscv\/\" \/>\n<meta property=\"og:locale\" content=\"fr_FR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"RISCV - workboot\" \/>\n<meta property=\"og:description\" content=\"Introduction \u00e0 RISC-V Qu’est-ce que RISC-V ? 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Origine Pourquoi RISC-V est important ? \u2705 Pas de royalties \u2192 Id\u00e9al pour les startups et l’innovation.\u2705 Flexibilit\u00e9 \u2192 Adaptable aux besoins (IoT, IA, supercalculateurs).\u2705 \u00c9cosyst\u00e8me en croissance \u2192 […]","og_url":"https:\/\/workboot.fr\/ciela\/riscv\/","og_site_name":"workboot","article_modified_time":"2025-07-25T09:31:41+00:00","twitter_misc":{"Dur\u00e9e de lecture estim\u00e9e":"2 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"WebPage","@id":"https:\/\/workboot.fr\/ciela\/riscv\/","url":"https:\/\/workboot.fr\/ciela\/riscv\/","name":"RISCV - workboot","isPartOf":{"@id":"https:\/\/workboot.fr\/ciela\/#website"},"datePublished":"2025-07-25T09:30:12+00:00","dateModified":"2025-07-25T09:31:41+00:00","inLanguage":"fr-FR","potentialAction":[{"@type":"ReadAction","target":["https:\/\/workboot.fr\/ciela\/riscv\/"]}]},{"@type":"WebSite","@id":"https:\/\/workboot.fr\/ciela\/#website","url":"https:\/\/workboot.fr\/ciela\/","name":"workboot","description":"Open Source, Open Minds ","publisher":{"@id":"https:\/\/workboot.fr\/ciela\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/workboot.fr\/ciela\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"fr-FR"},{"@type":"Organization","@id":"https:\/\/workboot.fr\/ciela\/#organization","name":"workboot","url":"https:\/\/workboot.fr\/ciela\/","logo":{"@type":"ImageObject","inLanguage":"fr-FR","@id":"https:\/\/workboot.fr\/ciela\/#\/schema\/logo\/image\/","url":"https:\/\/workboot.fr\/ciela\/wp-content\/uploads\/2025\/05\/logo_ciel-dorian-1.png","contentUrl":"https:\/\/workboot.fr\/ciela\/wp-content\/uploads\/2025\/05\/logo_ciel-dorian-1.png","width":1024,"height":950,"caption":"workboot"},"image":{"@id":"https:\/\/workboot.fr\/ciela\/#\/schema\/logo\/image\/"}}]}},"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false},"uagb_author_info":{"display_name":"admin","author_link":"https:\/\/workboot.fr\/ciela\/author\/admin\/"},"uagb_comment_info":0,"uagb_excerpt":"Introduction \u00e0 RISC-V Qu’est-ce que RISC-V ? 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