{"id":5669,"date":"2025-12-07T10:52:19","date_gmt":"2025-12-07T09:52:19","guid":{"rendered":"https:\/\/workboot.fr\/ciela\/?page_id=5669"},"modified":"2025-12-11T10:05:11","modified_gmt":"2025-12-11T09:05:11","slug":"gd32vf103-user-manuel-v1-2","status":"publish","type":"page","link":"https:\/\/workboot.fr\/ciela\/gd32vf103-user-manuel-v1-2\/","title":{"rendered":"GD32VF103 User Manuel V1.2"},"content":{"rendered":"\n<nav aria-label=\"Table des mati\u00e8res\" class=\"wp-block-table-of-contents\"><ol><li><a class=\"wp-block-table-of-contents__entry\" href=\"https:\/\/workboot.fr\/ciela\/gd32vf103-user-manuel-v1-2\/#details-techniques-du-longan-nano\">D\u00e9tails techniques du Longan Nano :<\/a><ol><li><a class=\"wp-block-table-of-contents__entry\" href=\"https:\/\/workboot.fr\/ciela\/gd32vf103-user-manuel-v1-2\/#microcontroleur-gd32vf103cbt6architecture-risc-v-32-bits\">Microcontr\u00f4leur : GD32VF103CBT6 Architecture : RISC-V 32 bits<\/a><\/li><li><a class=\"wp-block-table-of-contents__entry\" href=\"https:\/\/workboot.fr\/ciela\/gd32vf103-user-manuel-v1-2\/#ensemble-d-instructions-rv32imacrv32i-entier-32-bits-de-base\">Ensemble d&rsquo;instructions : RV32IMAC RV32I : Entier 32 bits de base<\/a><\/li><li><a class=\"wp-block-table-of-contents__entry\" href=\"https:\/\/workboot.fr\/ciela\/gd32vf103-user-manuel-v1-2\/#c-est-pourquoi-on-compile-avec\">C&rsquo;est pourquoi on compile avec\u00a0:<\/a><\/li><li><a class=\"wp-block-table-of-contents__entry\" href=\"https:\/\/workboot.fr\/ciela\/gd32vf103-user-manuel-v1-2\/#difference-avec-risc-v-64-bits\">Diff\u00e9rence avec RISC-V 64 bits\u00a0:<\/a><\/li><\/ol><\/li><li><a class=\"wp-block-table-of-contents__entry\" href=\"https:\/\/workboot.fr\/ciela\/gd32vf103-user-manuel-v1-2\/#datasheet-officiel\">Datasheet officiel:<\/a><\/li><\/ol><\/nav>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"details-techniques-du-longan-nano\">D\u00e9tails techniques du Longan Nano :<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"microcontroleur-gd32vf103cbt6architecture-risc-v-32-bits\">Microcontr\u00f4leur : GD32VF103CBT6<br>Architecture : RISC-V 32 bits<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">C\u0153ur : Nuclei N308 (bas\u00e9 sur RV32IMAC)<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Fr\u00e9quence : 108 MHz max<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Flash : 128 KB (certaines versions 64 KB)<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">RAM : 32 KB (certaines versions 20 KB)<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"ensemble-d-instructions-rv32imacrv32i-entier-32-bits-de-base\">Ensemble d&rsquo;instructions : RV32IMAC<br>RV32I : Entier 32 bits de base<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">M : Multiplication\/division mat\u00e9rielle<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">A : Op\u00e9rations atomiques<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">C : Instructions compress\u00e9es (16 bits)<\/p>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"c-est-pourquoi-on-compile-avec\"><strong>C&rsquo;est pourquoi on compile avec<\/strong>\u00a0:<\/h3>\n\n\n\n<pre class=\"wp-block-code\"><code>-march=rv32imac   # Architecture RV32IMAC\n-mabi=ilp32       # ABI 32 bits (int, long, pointer = 32 bits)<\/code><\/pre>\n\n\n\n<h3 class=\"wp-block-heading\" id=\"difference-avec-risc-v-64-bits\"><strong>Diff\u00e9rence avec RISC-V 64 bits<\/strong>&nbsp;:<\/h3>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><thead><tr><th class=\"has-text-align-left\" data-align=\"left\">Aspect<\/th><th class=\"has-text-align-left\" data-align=\"left\">RV32 (Longan Nano)<\/th><th class=\"has-text-align-left\" data-align=\"left\">RV64<\/th><\/tr><\/thead><tbody><tr><td>Registres<\/td><td>32 bits<\/td><td>64 bits<\/td><\/tr><tr><td>Adressage<\/td><td>4 Go max<\/td><td>16 Eo max<\/td><\/tr><tr><td><code>-march<\/code><\/td><td><code>rv32imac<\/code><\/td><td><code>rv64imac<\/code><\/td><\/tr><tr><td><code>-mabi<\/code><\/td><td><code>ilp32<\/code><\/td><td><code>lp64<\/code><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"datasheet-officiel\">Datasheet officiel:<\/h2>\n\n\n\n<div data-wp-interactive=\"core\/file\" class=\"wp-block-file\"><object data-wp-bind--hidden=\"!state.hasPdfPreview\" hidden class=\"wp-block-file__embed\" data=\"https:\/\/workboot.fr\/ciela\/wp-content\/uploads\/2025\/12\/GD32VF103_User_Manual_EN_V1.2.pdf\" type=\"application\/pdf\" style=\"width:100%;height:600px\" aria-label=\"Contenu embarqu\u00e9 GD32VF103_User_Manual_EN_V1.2.\"><\/object><a id=\"wp-block-file--media-b8dbda64-1225-4e80-b37f-68c8277059a2\" href=\"https:\/\/workboot.fr\/ciela\/wp-content\/uploads\/2025\/12\/GD32VF103_User_Manual_EN_V1.2.pdf\">GD32VF103_User_Manual_EN_V1.2<\/a><a href=\"https:\/\/workboot.fr\/ciela\/wp-content\/uploads\/2025\/12\/GD32VF103_User_Manual_EN_V1.2.pdf\" class=\"wp-block-file__button wp-element-button\" download aria-describedby=\"wp-block-file--media-b8dbda64-1225-4e80-b37f-68c8277059a2\">T\u00e9l\u00e9charger<\/a><\/div>\n","protected":false},"excerpt":{"rendered":"<p>D\u00e9tails techniques du Longan Nano : Microcontr\u00f4leur : GD32VF103CBT6Architecture : RISC-V 32 bits C\u0153ur : Nuclei N308 (bas\u00e9 sur RV32IMAC) Fr\u00e9quence : 108 MHz max Flash : 128 KB (certaines versions 64 KB) RAM : 32 KB (certaines versions 20 KB) Ensemble d&rsquo;instructions : RV32IMACRV32I : Entier 32 bits de base M : Multiplication\/division mat\u00e9rielle [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_uag_custom_page_level_css":"","footnotes":""},"class_list":["post-5669","page","type-page","status-publish","hentry"],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false},"uagb_author_info":{"display_name":"admin","author_link":"https:\/\/workboot.fr\/ciela\/author\/admin\/"},"uagb_comment_info":0,"uagb_excerpt":"D\u00e9tails techniques du Longan Nano : Microcontr\u00f4leur : GD32VF103CBT6Architecture : RISC-V 32 bits C\u0153ur : Nuclei N308 (bas\u00e9 sur RV32IMAC) Fr\u00e9quence : 108 MHz max Flash : 128 KB (certaines versions 64 KB) RAM : 32 KB (certaines versions 20 KB) Ensemble d&rsquo;instructions : RV32IMACRV32I : Entier 32 bits de base M : Multiplication\/division mat\u00e9rielle\u2026","_links":{"self":[{"href":"https:\/\/workboot.fr\/ciela\/wp-json\/wp\/v2\/pages\/5669","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/workboot.fr\/ciela\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/workboot.fr\/ciela\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/workboot.fr\/ciela\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/workboot.fr\/ciela\/wp-json\/wp\/v2\/comments?post=5669"}],"version-history":[{"count":6,"href":"https:\/\/workboot.fr\/ciela\/wp-json\/wp\/v2\/pages\/5669\/revisions"}],"predecessor-version":[{"id":5746,"href":"https:\/\/workboot.fr\/ciela\/wp-json\/wp\/v2\/pages\/5669\/revisions\/5746"}],"wp:attachment":[{"href":"https:\/\/workboot.fr\/ciela\/wp-json\/wp\/v2\/media?parent=5669"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}